Modern day integrated chips are comprised of a very large number of semiconductor devices having microscopic dimensions. Operation of the semiconductor devices comprised within an integrated chip depend upon a robust system of electrical connections between the semiconductor devices and the outside world. These electrical connections are formed by a complex configuration of metal interconnect levels (i.e., metal levels; metal wire levels) that electrically interconnect various semiconductor devices of an integrated chip to each other and to an external power supply.
FIG. 1 shows an integrated chip's metal interconnect levels commonly referred to as a back end of the line (BEOL) metallization stack 100. The metallization stack comprises a vertical hierarchy of alternating metal levels (M1, M2, M3, M4) and via (i.e., stud) levels (V1, V2, V3) comprised within an inter-level dielectric material 102 having a low dielectric constant. The metal levels (M1, M2, M3, M4) provide horizontal interconnections between semiconductor devices 104, while the vias (V1, V2, V3) provide vertical interconnections between various layers of the horizontal metal levels (e.g., V1 provides an interconnection between M1 and M2). The inter-level dielectric material 102 is comprised of a plurality of dielectric layers (108, 110, 112, 114, 116) that provide physical support, electrical insulation, and electrical isolation between the metal and via levels.
The alternating metal and via levels typically increase in minimum horizontal dimension (e.g., metal line thickness) and vertical dimension (e.g., metal line height) as they appear vertically higher in the stack (e.g., thinner metal wire M1 is located below thicker metal wires M3 and M4). For example, as shown in FIG. 1, thin metal level M1 is connected to respective semiconductor devices 104 by way of a conductive contact 106. Thin metal level M1 is also connected by via V1 to thicker metal level M2 located vertically above the thin metal level M1. The thickest metal levels are typically coupled to a wirebond or flip-chip packaging through which electrical impulses can be transmitted to semiconductor devices of the integrated chip. In general, thin metal levels (i.e., metal wires having a relatively small critical dimension with respect to other metals in the same stack) are configured to carry small currents and to connect to thicker metal levels configured to carry larger currents. This hierarchy allows thick metal levels to carry power to a large number of semiconductor devices via the thin metal levels.
Metal wire levels and via levels are fabricated using separate lithography and etch steps. Using a dual damascene process, fabrication of the metal and via levels comprises forming a metal and via level within a deposited inter-level dielectric (ILD) material layer (e.g., silicon oxide, fluorinated silicon oxide, polymers including polyimide and fluorinated polyimide, ceramics, carbon and other dielectric materials). During processing, the ILD layer is deposited and then holes (i.e., via holes) are patterned using known techniques such as the use of a photoresist material which is exposed to define a pattern. After developing, the photoresist acts as a mask through which the pattern of the ILD material is removed by a subtractive etch process (e.g., such as plasma etching or reactive ion etching) to partially form the via holes. A second patterning process proceeds to pattern metal wires within the ILD layer. The pattern is also removed through a subtractive etch process which forms metal trenches and completes via hole etching such that the via holes extend from the top surface of the ILD layer to the bottom surface of the ILD layer, while the metal trenches are comprised within the upper part of the ILD layer. The via holes and metal trenches are then filled in a single metal deposition step to form both a via level and a vertically abutting metal layer (e.g., the metal layer above the via). Metal may be deposited using a filling technique such as electroplating, electroless plating, chemical vapor deposition, physical vapor deposition or a combination of methods. This process may further include planarization of the metal by removing excess material with a method such as chemical mechanical polishing (CMP).
FIG. 1 illustrates a dual damascene structure wherein via level V1 (or V2, or V3) and metal layer M2 (or M3, or M4) are formed by a single metal deposition in the same dielectric layer 112 (or 114, or 116). Dual damascene processing results in a simplified processing flow (e.g., one less deposition step, one less CMP step) and greater reliability (e.g., robust interconnection between metal and via lines within the same dielectric layer) than single damascene processing.